1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit memory arrays and, more particularly, to static random access memory arrays formed at extremely high integration density.
2. Description of the Prior Art
Increased integration density yields advantages in performance and functionality of integrated circuits as well as increased economy of manufacture since reduced size of electronic elements, such as transistors, allows a greater number of such elements to be formed on a chip of a given size while increased proximity between devices allows reductions in signal propagation time. In regard to integrated circuit memory arrays, increased integration density allows more data to be stored per chip and potential improvements in operating margins. Therefore, there is a strong incentive toward manufacture of integrated circuit memories at reduced minimum feature size regimes.
The minimum feature size is an extremely important parameter of the design rules for a given integrated circuit. The minimum feature size refers to the minimum allowed transverse dimension for a lithographically defined feature (although the current state of the art allows some structures, such as transistor gate sidewalls, to be formed at sub-lithographic dimensions) and also applies to the minimum permitted spacing between features such as wiring. In general, conductors must be formed in segments in a metallization layer while another layer is used to connect the segments though contact vias in an intervening insulation layer. Such a structure requires high accuracy of registration between the metal layers and the contact locations between them. Therefore, there is a trade-off between greater spacing between conductive segments in any layer to increase registration tolerance and the ultimate integration density that can be achieved. Accordingly, space between conductors is generally made very close to the minimum feature size even though manufacturing yield may be somewhat compromised.
Further, since the minimum feature size is necessarily limited by lithographic resolution, the features of the lithographic images will be degraded somewhat by rounding and foreshortening of ends of conductors, particularly as minimum feature size is reduced. Because conductors extend between connection locations (e.g. vias) foreshortening or rounding of the ends of conductors may reduce the area of the conductor which overlaps the connection structure and potentially result in an open circuit unless the lithographic image is adjusted to increase dimensions at the ends of conductors so that the overlap area will not be significantly reduced.
Such an adjustment is referred to as an optical proximity correction (OPC) anchor and necessarily reduces the distance between conductors, at least in the image used to expose the lithographic resist, so that the intended spacing will be substantially restored in the resulting conductor shape. Increase of conductor length beyond a connection structure by an OPC anchor is referred to as an extension and an increase of width of a conductor by an OPC anchor at a connection structure is referred to as a tab. Tabs and extensions may be used independently or in combination. Such aggressive design reduces the lithographic process window and compromises manufacturing yield.
It is also generally the case that such aggressive design spaces require adjustment of routing of other connections, often requiring segments of connections to be run diagonally. Diagonal segments are more difficult to expose lithographically since they require angled shapes to be produced and, in general, imply that other space on the chip will be used less than optimally. Diagonal conductors may also imply other complications of layout to limit capacitive coupling to other elements of the integrated circuit.
Another complication of circuit layout for static random access memories (SRAMs) is the need to provide power to the active devices in the cell which form a bistable circuit which comprises a memory cell as well as connections to carry stored data signals to and from the cell and provide for cell selection. At the current state of the art, it is generally preferred to provide data in both true and inverse logic states over a selected pair of bit lines and to use an additional word line, orthogonal to the selected bit line pair, for cell selection. A power supply line (VDD) and a power return path (e.g. GND) must also be provided. These five connections to each cell complicate the design layout over large arrays because of the connections which must be made between the power supply and return lines for many rows (or columns) of memory cells in order to limit voltage drops across the array and to assure that all cells of the array receive substantially the same voltage at all times. In general, arrangement of memory cells in mirrored pairs has provided some simplification of these connections but many segments of power supply conductors and a large number of I/O pins are required for satisfactory operation and operating margins.
It is therefore an object of the present invention to provide a memory cell layout having improved connection coverage/overlap with improved manufacturing yield.
It is another object of the invention to provide a memory cell array in which the size of memory cell can fully exploit the minimum feature size of the design rules without significant compromise of manufacturing yield.
It is a further object of the invention to provide a memory cell array having a reduced number of internal and external connections to the chip.
In order to accomplish these and other objects of the invention, a static memory cell is provided including a bistable circuit, a first power connection to the bistable circuit having a first end abutting a first side of the memory cell and a second end abutting a second side of said memory cell adjacent the first side of the memory cell, and a second power connection to the bistable circuit having a first end abutting a third side of the memory cell and a second end terminated at a via within the memory cell.
In accordance with another aspect of the invention, a memory array is provided including a serpentine power connection shared between memory cells of adjacent rows of memory cells of said memory array, and a further power connection shared between memory cells of adjacent columns of memory cells of said memory array.